This invention relates to a method of direct memory access control for a system comprising input/output devices, a memory and a control processor, such as an electronic switching system, in which the input/output devices send direct memory access requests to the processor.
The direct memory access control between input/output devices and a processor is described, for example, in an article entitled "Architecture of a Distributed Packet Switching System", in the publication "Switching Research", SE84-121, pp. 37-42. In this packet switching system, the line unit as an input/output device has the ability to perform direct memory access. The line unit (input/output device), when making direct memory access, sends a processor bus holding request signal to the processor. Upon receiving the request signal, the processor holds the processor bus which connects the line units to the processor regardless of the time needed for the transmission of direct memory access information (memory address and data) between the line unit and processor, and thereafter grants the line unit a direct memory access to the memory.
In this case, if the transmission of direct memory access information between the line unit and the processor takes a long time, the processor holds the processor bus for a long time at the execution of direct memory access, and therefore the processor cannot access the memory during this period, resulting in a reduction in the processing speed of the processor.